Prof. Ashutosh Kumar Singh

Dr. Ashutosh Kumar Singh obtained his Ph. D. degree in Electronics Engineering from Indian Institute of Technology, BHU, India and Post Doc from Department of Computer Science, University of Bristol, UK. He has status of Charted Engineer from IET, UK.

 

His research area includes Verification, Synthesis, Design and Testing of Digital Circuits. He has published more than 110 research papers till now in different journals, conferences and news magazines and in these areas. He is a co-author of five books  Web Spam Detection Application using Neural Network “Digital Systems Fundamentals” and “Computer System Organization & Architecture”. I have worked as principal investigator for four sponsored research projects and was a key member on a project from EPSRC (UK) “Logic Verification and Synthesis in New Framework”.

 

He had delivered the invited talks and presented research papers in several countries including Australia, UK, South Korea, China, Thailand, Indonesia, India and USA. He had been entitled for the several awards such as Merit Award-03 (Institute of Engineers), Best Poster Presenter-99 in 86th Indian Science Congress held in Chennai, INDIA, Best Paper Presenter of NSC’99 INDIA.

 

Currently he is an Editorial Board Member of International Journal of Networks and Mobile Technologies, International journal of Digital Content Technology and its Applications. Also has shared his experience as an Guest Editor for Pertanika Journal of Science and Technology, Chairman of CUTSE International Conference 2011 and as editorial board member of UNITAR e-journal. He is involved in reviewing process in different journals and conferences such as; IEEE transaction of computer, IET, IEEE conference on ITC, ADCOM etc.

 

Presently he is leading two research grants and supervising eight Higher Degree Research students. He has worked as a Principal Investigator on a research project “Application of Decision Diagrams in Synthesis, Design and Testing of VLSI” in Malaysia. He was a key member on a project from EPSRC (UK) “Logic Verification and Synthesis in New Framework”.